In the processing of integrated circuits, electrical contact must be made to isolated active device regions formed within a wafer substrate typically comprising monocrystalline. The active device regions are connected by highly conductive paths or lines which are fabricated above the wafer substrate in insulative material which covers the substrate surface. To provide electrical connection between the conductive path and active device regions, an opening in the insulator is provided to enable conductive material to contact the desired regions. Such openings are typically referred to as contact openings or simply contacts.
In an effort to substantially reduce or otherwise eliminate shallow junction leakage in the contact areas, fabricators of semiconductive devices have utilized polysilicon plugs. Following the formation of these plugs, fabricators have utilized an additional masking step to further define the polysilicon plug. This additional masking step insures, to some degree, that subsequent contact openings will be formed in a manner to open and land completely on the underlying polysilicon plug. As integrated circuits have decreased in size, it becomes increasingly difficult to properly align masks such that subsequent contact openings are formed properly, that is, which land completely on the underlying polysilicon plug.
A method which eliminates the need to have an additional masking step and also provides a means by which subsequent contact openings can be formed to land substantially on the underlying polysilicon plug is the subject matter of the present application.